1. Field of The Invention
The present invention relates generally to a semiconductor memory device and a method for producing the same. More specifically, the invention relates to a semiconductor memory device which is used as a random access memory (RAM) having trench capacitors.
2. Related Background Art
Currently, RAMs having trench capacitors as cell capacitors are widely used. FIG. 22 shows a plan view of such a RAM, and FIG. 23 shows a sectional view taken along line A--A of FIG. 22. Memory cells connected to each bit line 50 are aligned with each other so that two adjacent memory cells serve as a set of memory cells. Cell transistors 30.sub.1, and 30.sub.2 serving as components of the memory cells of the same set have a common drain 35b, to which the bit line is connected via a contact 55 (see FIG. 2). To sources 35a, and 35a.sub.2 of the cell transistors 30.sub.1, and 30.sub.2, trench capacitors 60.sub.1, and 60.sub.2 are connected. Gate electrodes 31.sub.i of the respective cell transistors 30.sub.i (i=1, 2) serve as word lines connected to the memory cells including the cell transistors 30.sub.i.
The trench capacitors of the adjacent set of memory cells connected to the same capacitor, e.g., the trench capacitors 60.sub.1, and 60.sub.3, are electrically isolated from each other by means of an insulator film 25. The trench capacitors 60.sub.1, 60.sub.2 and 60.sub.3 of the memory cells connected to the same bit line are aligned with each other.
Over the respective trench capacitors 60.sub.1 (i=1, 2, 3), pass-word lines 33.sub.i are provided. The pass-word lines 33.sub.i (i=1, 2, 3) serve as word lines for memory cells connected to a bit line adjacent to the bit line 50, to which the memory cells including the trench capacitors 60.sub.i are connected.
FIG. 21 shows a sectional view of a memory cell of a conventional RAM having trench capacitors as cell capacitors of the memory cell. The RAM has a plurality of memory cells. Each of the memory cells has a cell transistor 30 and a trench capacitor 60. The cell transistor 30 has a gate electrode 31 formed on a p-type silicon substrate 1 via a gate insulator film 29, and a source region 35a and a drain region 35b which are n-type diffusion regions formed in the silicon substrate 1 so that the gate electrode 31 is sandwiched by the source region 35a and the drain region 35b.
On the other hand, the trench capacitor 60 comprises a capacitor insulator film 7 formed on the wall surface of a trench provided in the silicon substrate 1, a storage node 9 of a polycrystalline silicon film buried in the trench, a storage node electrode 41 of a polycrystalline silicon film formed on the storage node 9, and a plate electrode 27 of an n-type diffusion layer formed in the silicon substrate 1. Furthermore, n-type impurities are added to the polycrystalline silicon films forming the storage node 9 and the storage node electrode 41.
The storage node electrode 41 is electrically connected to the source electrode 35a of the cell transistor 30 via a side wall contact 42. Furthermore, on the side portions of the lower portion of the storage node electrode 41, a thick insulator film 40 is formed to prevent a vertical parasitic transistor from being formed. On the upper portion of the storage node electrode 41, an insulator film 44 is formed to electrically isolate the storage node electrode 41 from the pass-word line provided above the trench capacitor 60. The trench capacitors of the adjacent memory cells are electrically isolated from each other by means of the insulator film 25.
In the conventional RAM with the above described construction, since the thick insulator film 44 is formed in the upper portion of the trench capacitor 60, the depth of the side wall contact 42 is great, so that the lower surface of the side wall contact 42 is arranged below the source region 35a. In such a state, a depletion layer of a p-n junction between a p-well 2 and the storage node 9 contacts the side wall contact 42. Therefore, a leak current increases, so that the charge holding characteristic of the memory cell deteriorates. Furthermore, it is conceived that the depth of the source region 35a is increased in order to prevent the charge holding characteristic from deteriorating. In this case, there is a problem in that the punchthrough withstand voltage of the cell transistor 30 deteriorates.